Perform functional verification of ASIC/IP blocks using constrained random simulation and assertion based formal verification methodology; develop, review, and execute comprehensive verification plans; generate and analyze functional and code coverage; define and implement functional coverage checkers; develop test bench and assertions; write directed and random test cases; and debug failure. Requirements – Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and three years of experience with functional verification or Bachelor’s degree and five years of post-baccalaureate and progressive experience in functional verification. Three years of experience with constrained random simulation, assertions based formal verification, Verilog, SystemVerilog, and OVM.
Please refer to Job Number ESE15-0203 when submitting resume.
Submit resume to:
Esencia Technologies, Inc.
2041 Mission College Blvd., Suite 100
Santa Clara, CA 95054
ATTN: Human Resources-Job No. ESE15-0203
E-mail: hr@esenciatech.com
